Embedded system for contrast enhancement in low-vision

Authors:
P. MartíNez CañAda;C. Morillas;R. UreñA;J. M. GóMez LóPez;F. J. Pelayo
Affiliations:
Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, C/Periodista Rafael Gómez Montero 2, E-18070 Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, C/Periodista Rafael Gómez Montero 2, E-18070 Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, C/Periodista Rafael Gómez Montero 2, E-18070 Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, C/Periodista Rafael Gómez Montero 2, E-18070 Granada, Spain;Department of Computer Architecture and Technology, CITIC, ETSIIT, University of Granada, C/Periodista Rafael Gómez Montero 2, E-18070 Granada, Spain
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2013

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Abstract

This paper presents a real-time contrast enhancement system, implemented in FPGA and adapted to display the processed images on a Head Mounted Display (HMD). A novel visual processing scheme is proposed which combines a version of the algorithm known as Contrast Limited Adaptive Histogram Equalization (CLAHE) with a spatial filtering based on a bio-inspired retina model. The system is designed so that visually impaired people can improve their functionality in environments with non-uniform lighting or with abrupt changes in lighting conditions. The parallelism offered by FPGA devices allow to achieve real-time processing with VGA-resolution images, reaching up to 60 frames per second. This system, developed on a FPGA of reduced complexity, has been compared in performance with a parallel implementation on a portable platform based on GPU.