Testing equivalences for event structures
Advanced School on Mathematical models for the semantics of parallelism
Theoretical Computer Science
A process algebra for timed systems
Information and Computation
MFCS '96 Proceedings of the 21st International Symposium on Mathematical Foundations of Computer Science
Automated Test Generation from Timed Automata
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Minimization of Timed Transition Systems
CONCUR '92 Proceedings of the Third International Conference on Concurrency Theory
Testing Equivalence as a Bisimulation Equivalence
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Testing Theories for Asynchronous Languages
Proceedings of the 18th Conference on Foundations of Software Technology and Theoretical Computer Science
An introduction to event structures
Linear Time, Branching Time and Partial Order in Logics and Models for Concurrency, School/Workshop
Analysis of Timed Concurrent Models Based on Testing Equivalence
Fundamenta Informaticae
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In verification of complex computing systems, the concept of testing equivalence is frequently used. One of the ways to solve the problem of recognizing timed testing equivalences in the framework of the model of timed event structures with internal actions is to reduce it to formula verification on a model (model-checking). To this end, logical formulas characterizing timed event structure up to test pre-orders are constructed. In the paper, composition methods for characteristic formulas that do not rely on region and class graphs are considered, which simplifies construction of the characteristic formulas.