Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach

  • Authors:

  • M. Portela-Garcia;A. Lindoso;L. Entrena;M. Garcia-Valderas;C. Lopez-Ongil;N. Marroni;B. Pianta;L. Bolzani Poehls;F. Vargas

  • Affiliations:

  • Electronic Technology Department, Carlos III University of Madrid, Madrid, Spain;Electronic Technology Department, Carlos III University of Madrid, Madrid, Spain;Electronic Technology Department, Carlos III University of Madrid, Madrid, Spain;Electronic Technology Department, Carlos III University of Madrid, Madrid, Spain;Electronic Technology Department, Carlos III University of Madrid, Madrid, Spain;School of Engineering, Catholic University of Rio Grande do Sul - PUCRS, Porto Alegre, Brazil;School of Engineering, Catholic University of Rio Grande do Sul - PUCRS, Porto Alegre, Brazil;School of Engineering, Catholic University of Rio Grande do Sul - PUCRS, Porto Alegre, Brazil;School of Engineering, Catholic University of Rio Grande do Sul - PUCRS, Porto Alegre, Brazil

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

Nowadays, microprocessor-based system's robustness under Single Event Effects (SEEs) represents a very important concern. A widely adopted solution to make a microprocessor-based system robust consists in modifying the application code by adding redundancy and fault tolerance capabilities. In this context, the main idea behind this paper is to evaluate a software-based technique named Optimized Embedded Signature Monitoring (OESM) using an FPGA-based fault injection technique, which is able to inject a high number of Single Event Upsets (SEUs) and Single Event Transients (SETs) in a short period of time. The obtained results demonstrated not only the increase of system's robustness level, but also point out the remaining weak areas in the microprocessor-based system with respect to both types of SEEs.