Search sequence determination for tree search based detection algorithms
SARNOFF'09 Proceedings of the 32nd international conference on Sarnoff symposium
Complexity reduced soft-in soft-out sphere detection based on search tuples
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
A scalable VLSI architecture for soft-input soft-output depth-first sphere decoding
IEEE Transactions on Circuits and Systems II: Express Briefs
A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Architecture design and implementation of the metric first list sphere detector algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
| Hi-index | 0.00 |
Achieving good detection performance while incurring low complexity is known to be one of the major challenges in multiple-input multiple-output (MIMO) communications based on spatial multiplexing. The tuple search detector (TSD) was recently introduced, improving this trade-off with regard to other tree-search-based algorithms (e.g. single tree search or list sphere detector). Motivated by the tremendous gain achievable through the turbo principle and based on a previously developed soft-output (SO) TSD implementation, this work presents the first soft-input soft-output (SISO) TSD realization, scalable in constellation size and number of antennas and mapped to a highly parallel and pipelined VLSI architecture. The proposed SISO-TSD VLSI realization is instantiated for 4 脳 4 MIMO transmission and 64-QAM constellation in 65-nm CMOS technology. For a given BER驴complexity trade-off, the throughput ranges from 57.3 Mbps (iterative detection-decoding with 3 iterations) to 403.6 Mbps (non-iterative detection-decoding) at a clock frequency of 454 MHz. The BER驴complexity trade-off can be moreover adjusted according to transmission conditions, reaching 1 Gbps in high SNR scenarios. A silicon area of 0.14 mm2 (97.7 kGEs) is occupied by the SISO-TSD core, reporting low power dissipation (58.2 mW --- 73.9 mW) under typical case operating conditions. The proposed detector implementation achieves hence high throughput with reasonable hardware complexity, representing a very competitive strategy with regard to relevant state-of-the-art realizations.