Effect of sample-timing error on performance of interleave-division multiple access systems
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
Interleave division multiple-access
IEEE Transactions on Wireless Communications
Iterative multiuser joint decoding: unified framework and asymptotic analysis
IEEE Transactions on Information Theory
Iterative multiuser joint decoding: optimal power allocation and low-complexity implementation
IEEE Transactions on Information Theory
Evolution analysis of low-cost iterative equalization in coded linear systems with cyclic prefixes
IEEE Journal on Selected Areas in Communications
Symbol Detection of IDMA Systems in the Presence of Carrier Frequency Offsets
Wireless Personal Communications: An International Journal
GLRT Approach for Performance Improvement in Practical Burst Packet Acquisition with AGC Amplifier
Wireless Personal Communications: An International Journal
Hi-index | 0.00 |
Sample-timing error can cause significant performance degradation for the interleave-division multiple-access systems (Wang et al. 2009). In this paper, we propose a non-data-aided timing acquisition scheme to mitigate sample-timing error due to the asynchronous transmission of random allocated user ends (UEs) on the uplink. A closed-loop timing control scheme is constructed for the asynchronous IDMA system in this paper. We use the extrinsic information generated during the iterative detection algorithm with signal noise ratio evolution to estimate the timing offset for the asynchronous uplink in the base station (BS) receiver. The BS receiver returns the timing control bits, which is generated with estimated timing offsets, to the corresponding UE. And the UE uses the timing control bits to adjust local transmission time to guarantee the sampling performance at the BS receiver. The simulation results show that the proposed acquisition scheme based on feedback loop can provide high acquisition probability and low false alarm probability. The proposed scheme can overcome the bit-error-rate performance bottleneck, which is caused by the sample-timing error in BS receiver due to the asynchronous signals in the uplink.