Reactive NUCA: near-optimal block placement and replication in distributed caches
Proceedings of the 36th annual international symposium on Computer architecture
Subspace snooping: filtering snoops with operating system support
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
SWEL: hardware cache coherence protocols to map shared data onto shared caches
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
Proceedings of the 38th annual international symposium on Computer architecture
POPS: Coherence Protocol Optimization for Both Private and Shared Data
PACT '11 Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques
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Embedded devices are becoming more and more present everywhere. Moreover, mobile devices are becoming also more computationally powerful. These embedded architectures present new challenges since they execute several applications that must preserve security, allow sharing information in a coherent way, to be scalable and provide the required levels of performance, while at the same time they must be power efficient. The virtical project focuses on these challenges. In this context, as a starting point, we tackle the characterization of applications targeted for the hardware platform developed, that is, a heterogeneous multicore SoC. The aim is to analyze memory sharing patterns in order to exploit them to make the coherence protocols more scalable and power-efficient. We have identified that 60% of the accessed blocks are data, and from those only 40% require coherence maintenance.