Theoretical Computer Science
Generating test cases for real-time systems from logic specifications
ACM Transactions on Computer Systems (TOCS)
Theoretical Computer Science
Timed Wp-Method: Testing Real-Time Systems
IEEE Transactions on Software Engineering
Mutation Testing Applied to Validate Specifications Based on Petri Nets
Proceedings of the IFIP TC6 Eighth International Conference on Formal Description Techniques VIII
Test Generation with Inputs, Outputs, and Quiescence
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
FTRTFT '96 Proceedings of the 4th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Automatic Test Generation for the Analysis of a Real-Time System: Case Study
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Fault Coverage in Testing Real-Time Systems
RTCSA '99 Proceedings of the Sixth International Conference on Real-Time Computing Systems and Applications
A new method for testing real time systems
RTCSA '00 Proceedings of the Seventh International Conference on Real-Time Systems and Applications
Timed Test Cases Generation Based on State Characterization Technique
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
On the Fly Test Generation for Real Time Protocols
IC3N '98 Proceedings of the International Conference on Computer Communications and Networks
Testing real-time embedded software using UPPAAL-TRON: an industrial case study
Proceedings of the 5th ACM international conference on Embedded software
A scalable method for testing real-time systems
Software Quality Control
QSIC '08 Proceedings of the 2008 The Eighth International Conference on Quality Software
Two Complementary Tools for the Formal Testing of Distributed Systems with Time Constraints
DS-RT '08 Proceedings of the 2008 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications
Conformance testing for real-time systems
Formal Methods in System Design
Towards an Industrial Strength Process for Timed Testing
ICSTW '09 Proceedings of the IEEE International Conference on Software Testing, Verification, and Validation Workshops
Model-based testing of a WAP gateway: an industrial case-study
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
A guided method for testing timed input output automata
TestCom'03 Proceedings of the 15th IFIP international conference on Testing of communicating systems
Fault Coverage Measurement of a Timed Test Case Generation Approach
ECBS '10 Proceedings of the 2010 17th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems
Testing real-time systems using UPPAAL
Formal methods and testing
GeTeX: A Tool for Testing Real-Time Embedded Systems Using CAN Applications
ECBS '11 Proceedings of the 2011 18th IEEE International Conference and Workshops on Engineering of Computer-Based Systems
Specifying and generating test cases using observer automata
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
An expressive and implementable formal framework for testing real-time systems
TestCom'05 Proceedings of the 17th IFIP TC6/WG 6.1 international conference on Testing of Communicating Systems
Conformance testing relations for timed systems
FATES'05 Proceedings of the 5th international conference on Formal Approaches to Software Testing
Specification Mutation Analysis for Validating Timed Testing Approaches Based on Timed Automata
COMPSAC '12 Proceedings of the 2012 IEEE 36th Annual Computer Software and Applications Conference
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Real-Time Embedded Systems (RTESs) have an increasing role in controlling the IT that we use on a day-to-day basis. The behaviour of an RTES is not based solely on the interactions it might have with its surrounding environment, but also on the timing requirements it induces. As a result, ensuring that an RTES behaves correctly is non-trivial, especially after adding time as a new dimension to the complexity of the testing process. We previously introduced the 'priority-based' approach which tests the logical and timing behaviour of an RTES modelled formally as UPPAAL automata. The 'priority-based' approach was based on producing sets of timed test traces by achieving clock region coverage. In this paper, we empirically validate the 'priority-based' approach with comparison to well-known timed testing approaches based on a Timed Automata (TA) formalism using a complete test bed based on an industrial-strength case study (production cell). The validation assessment is based on both fault coverage and structural coverage by a minimal number of generated test traces; the former is achieved using the Mutation Analysis Technique (MAT) by introducing a set of timed and functional mutation operators. The latter is based on clock region coverage as a main timed structural coverage criterion. This study shows that 'priority-based' approach can combine a high fault coverage and clock region coverage with a relatively small number of test traces in comparison with other test approaches. A set of experiences and lessons learned are highlighted as result of the real-time test bed.