An algorithm for fast multiplication of sedenions

Authors:
Aleksandr Cariow;Galina Cariowa
Affiliations:
West Pomeranian University of Technology, Szczecin, Department of Computer Architectures and Telecommunications, ul. Zolnierska 49, 71-210 Szczecin, Poland;West Pomeranian University of Technology, Szczecin, Department of Computer Architectures and Telecommunications, ul. Zolnierska 49, 71-210 Szczecin, Poland
Venue:
Information Processing Letters
Year:
2013

Citing 4
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Abstract

In this work a rationalized algorithm for calculating the product of sedenions is presented which reduces the number of underlying multiplications. Therefore, reducing the number of multiplications in VLSI processor design is usually a desirable task. The computation of a sedenion product using the naive method takes 256 multiplications and 240 additions, while the proposed algorithm can compute the same result in only 122 multiplications (or multipliers - in hardware implementation case) and 298 additions.