Signal integrity and propagation delay analysis using FDTD technique for VLSI interconnects
Journal of Computational Electronics
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Accurate time domain analysis and cross talk estimation in VLSI interconnects has emerged as an essential design criteria. This paper presents the description of a finite difference time domain (FDTD) method that is intended for estimation of voltages and currents on coupled transmission line. A numerical method based on FDTD is opted for the estimation of cross talk induced time delay in lossy RLC interconnects. Both functional and dynamic cross talk effects in coupled line configuration are analyzed. Effect of line resistance on delay is also evaluated. A linear resistive driver is used to drive distributed RLC transmission line for lossy interconnect. It has been observed that the analytical results for proposed FDTD model are in good agreement with HSPICE simulation results. The proposed model using FDTD results in an average error of 4.1% with respect to HSPICE.