A hardware-efficient architecture for embedded real-time cascaded support vector machines classification

  • Authors:

  • Christos Kyrkou;Theocharis Theocharides;Christos Savvas Bouganis

  • Affiliations:

  • University of Cyprus & KIOS Research Center, Nicosia, Cyprus;University of Cyprus & KIOS Research Center, Nicosia, Cyprus;Imperial College London, London, England UK

  • Venue:
  • Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
  • Year:
  • 2013

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Abstract

This work presents an optimized architecture for cascaded SVM processing, along with a hardware reduction method for the implementation of the additional stages in the cascade, leading to significant improvements. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources, with only 0.7% reduction in classification accuracy.