Introduction to programmable active memories
Systolic array processors
Loop fusion and temporal common subexpression elimination in window-based loops
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Programmable Active Memories: A Performance Assessment
Proceedings of the First Heinz Nixdorf Symposium on Parallel Architectures and Their Efficient Use
Input data reuse in compiling window operations onto reconfigurable hardware
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Efficient hardware code generation for FPGAs
ACM Transactions on Architecture and Code Optimization (TACO)
Compiled acceleration of c programs on fpgas
Compiled acceleration of c programs on fpgas
Designing Modular Hardware Accelerators in C with ROCCC 2.0
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Impact of high-level transformations within the ROCCC framework
ACM Transactions on Architecture and Code Optimization (TACO)
OmpSs@Zynq all-programmable SoC ecosystem
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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FPGA-based accelerators have repeatedly demonstrated superior speed-ups on an ever-widening spectrum of applications. However, their use remains beyond the reach of traditionally trained applications code developers because of the complexity of their programming tool-chain. Compilers for high-level languages targeting FPGAs have to bridge a huge abstraction gap between two divergent computational models: a temporal, sequentially consistent, control driven execution in the stored program model versus a spatial, parallel, data-flow driven execution in the spatial hardware model. In this paper we discuss these challenges to the compiler designer and report on our experience with the ROCCC toolset.