Robust low-sensitivity Adaline neuron based on Continuous Valued Number System
Analog Integrated Circuits and Signal Processing
Comparison between analog and digital neural network implementations for range-finding applications
IEEE Transactions on Neural Networks
Scalable closed-boundary analog neural networks
IEEE Transactions on Neural Networks
An Experimental Study on Nonlinear Function Computation for Neural/Fuzzy Hardware Design
IEEE Transactions on Neural Networks
A Pyramidal Neural Network For Visual Pattern Recognition
IEEE Transactions on Neural Networks
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An important part of any hardware implementation of artificial neural networks (ANNs) is realization of the activation function which serves as the output stage of each layer. In this work, a new NMOS/PMOS design is proposed for realizing the sigmoid function as the activation function. Transistors in the proposed neuron are biased using only one biasing voltage. By operating in both triode and saturation regions, the proposed neuron can provide an accurate approximation of the sigmoid function. The neuron circuit is designed and laid out in 90-nm CMOS technology. The proposed neuron can be potentially used in implementation of both analog and hybrid ANNs.