A low-power low-cost design of primary synchronization signal detection

  • Authors:

  • Chixiang Ma;Hao Cao;Ping Lin

  • Affiliations:

  • Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, China;Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, China;Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, China

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2012

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Abstract

Synchronization is an important component of a practical communication system. Furthermore, network entry including synchronization is important. Since the detection of primary synchronization signal (PSS) is the first step of network entry in long term evolution (LTE) systems, thus it may be a critical path for practical systems. Therefore, tradeoff between performance and low power consumption and low cost of PSS detection needs to be made carefully. This paper presents a new synchronization method for low power and low cost design. The approach of a 1-bit analog-to-digital converter (ADC) with down-sampling is compared with that of a 10-bit ADC without down-sampling under multi-path fading conditions defined in LTE standard for user equipment (UE) performance test [5]. The simulation results of PSS are obtained on several kinds of channels. The simulation results explicitly show that the performance of the method with down-sampling for 1-bit ADC does not degrade even if frequency offset exists. Based on the simulation results, different implementation architectures and their synthesis report and analysis are present. A low-power low-cost design with high performance to detect PSS is derived in this paper.