The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-specific instruction set processor implementation of list sphere detector
EURASIP Journal on Embedded Systems
System architecture and implementation of MIMO sphere decoders on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Architecture design and implementation of the increasing radius - List sphere detector algorithm
ICASSP '09 Proceedings of the 2009 IEEE International Conference on Acoustics, Speech and Signal Processing
Low-complexity decoding via reduced dimension maximum-likelihood search
IEEE Transactions on Signal Processing
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector
Proceedings of the Conference on Design, Automation and Test in Europe
Design and implementation of a sort-free K-best sphere decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
IEEE Transactions on Signal Processing - Part I
A universal lattice code decoder for fading channels
IEEE Transactions on Information Theory
On maximum-likelihood detection and the search for the closest lattice point
IEEE Transactions on Information Theory
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
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In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4×4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps.