Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
Principles of mobile communication (2nd ed.)
Principles of mobile communication (2nd ed.)
Microwave Mobile Communications
Microwave Mobile Communications
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA-based accelerator for the verification of leading-edge wireless systems
Proceedings of the 46th Annual Design Automation Conference
A single FPGA filter-based multipath fading emulator
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Simulation of Nakagami fading channels with arbitrary cross-correlation and fading parameters
IEEE Transactions on Wireless Communications
Gaussian class multivariate Weibull distributions: theory and applications in fading channels
IEEE Transactions on Information Theory
A decomposition technique for efficient generation of correlated Nakagami fading channels
IEEE Journal on Selected Areas in Communications
Hardware Implementation of Rayleigh and Ricean Variate Generators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An efficient implementation of Nakagami-m and Weibull variate generators on a single field-programmable gate array (FPGA) is presented. The hardware model first generates a correlated Rayleigh fading variate sequence and then transforms it into a sequence of Nakagami-m or Weibull fading variates. A biquad processor facilitates the compact implementation of a Rayleigh variate generator with arbitrary autocorrelation properties. A combination of logarithmic and linear domain segmentations along with piece-wise linear approximations is used to accurately implement the nonlinear numerical functions required to transform the correlated Rayleigh fading process into Nakagami-m or Weibull fading processes. When implemented on a Xilinx Virtex-5 5VSX240TFF1738-2 FPGA, the fading simulator uses only 1.6% of the configurable slices, 1.2% of the DSP48E modules and 3 block memories, while operating at 120 MHz, generating 120 million complex variates per second. The throughput can be increased up to 373 MHz with this FPGA if two separate clock sources are utilized.