Pragmatic integration of an SRAM row cache in heterogeneous 3-D DRAM architecture using TSV

  • Authors:
  • Dong Hyuk Woo;Nak Hee Seong;Hsien-Hsin S. Lee

  • Affiliations:
  • Intel Labs, Intel Corporation, Santa Clara, CA;School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA;School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 2013

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Abstract

As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues--that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous DRAM chip provides a unique, promising opportunity for computer architects to contemplate a new memory hierarchy for future system design. In this paper, we study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency. In particular, we found that, if we want to design an SRAM row cache in a DRAM chip, simple stacking alone cannot address the majority of traditional SRAM row cache design issues. In this paper, to address these issues, we propose a novel floorplan and several architectural techniques that fully exploit the benefits of 3-D stacking technology. Our multi-core simulation results with memory-intensive applications suggest that, by tightly integrating a small row cache with its corresponding DRAM array, we can improve performance by 30% while saving dynamic energy by 31%.