Noncooperative cellular wireless with unlimited numbers of base station antennas
IEEE Transactions on Wireless Communications
Coordinated Multi-Point in Mobile Communications: From Theory to Practice
Coordinated Multi-Point in Mobile Communications: From Theory to Practice
Multiple Antenna Broadcast Channels With Shape Feedback and Limited Feedback
IEEE Transactions on Signal Processing - Part I
On the achievable throughput of a multiantenna Gaussian broadcast channel
IEEE Transactions on Information Theory
Dirty-paper coding versus TDMA for MIMO Broadcast channels
IEEE Transactions on Information Theory
Achievable rates in cognitive radio channels
IEEE Transactions on Information Theory
Achieving high data rates in a distributed MIMO system
Proceedings of the 18th annual international conference on Mobile computing and networking
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We present USC SDR, a wireless platform designed for easy-to-program, high data rate, real time wireless experimentation. The design of our platform aims at removing most of the bottlenecks encountered in the design of current software radio architectures, e.g. the requirement to program new schemes in an FPGA, and the difficulty to run real-time experiments for a long time. The architecture combines generic PCI FPGA development boards with radio front-ends built as self-sufficient daughterboards. The daughterboards are connected to the FPGAs, which in turn are plugged into the PCIE slots of a general-purpose server. Interestingly, the connection of the daughterboards to the FPGA cards is implemented through a standard FMC (FPGA Mezzanine Card) interface, such that the same RF front-end can be reused with future FPGA generations. In this way, USC SDR is not limited to a specific FPGA choice and does not require a complete re-design in order to accommodate for future more powerful FPGAs. The hardware is supported by a real-time software architecture where signal processing tasks, PHY and MAC layer algorithms can be programmed as user-level applications. As an example, we will showcase a massive MIMO testbed built using a single server with multiple PCIE slots.