Verifying timing synchronization constraints in distributed embedded architectures

Authors:
A. C. Rajeev;Swarup Mohalik;S. Ramesh
Affiliations:
Global General Motors R&D, India Science Lab, Bangalore, India;Global General Motors R&D, India Science Lab, Bangalore, India;Global General Motors R&D, India Science Lab, Bangalore, India
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 7
Cited 0

A theory of timed automata

Theoretical Computer Science
Guaranteeing Real-Time Requirements With Resource-Based Calibration of Periodic Processes

IEEE Transactions on Software Engineering
The theory of hybrid automata

LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Verifying temporal constraints on data in multi-rate transactions using timed automata

RTCSA '00 Proceedings of the Seventh International Conference on Real-Time Systems and Applications
Resource Conscious Design of Distributed Real-Time Systems: An End-to-End Approach

ICECCS '96 Proceedings of the 2nd IEEE International Conference on Engineering of Complex Computer Systems
Schedulability and end-to-end latency in distributed ECU networks: formal modeling and precise estimation

EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Timing analysis of distributed end-to-end task graphs with model-checking

EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Correct functioning of automotive embedded controllers requires hard real-time constraints on a number of system parameters. To avoid costly design iterations, these timing constraints should be verified during the design stage itself. In this paper, we describe a formal verification technique for a class of timing constraints called timing synchronization constraints in the recent adaptation of AUTOSAR standard (WPII-1.2 Timing Subgroup, Release 4.0). These constraints require, unlike the well studied end-to-end latency constraint, simultaneous analysis of multiple task/message chains or multiple data items traversing through a task/message chain. We show that they can be analyzed by model-checking with finite-state monitors. We also demonstrate this method on a case-study from the automotive domain.