MSSM—a design aid for multi-stage systolic mapping
Journal of VLSI Signal Processing Systems - Special issue: 1990 Workshop on VLSI signal processing
Uniformization of Affine Dependance Programs for Parallel Embedded System Design
ICPP '02 Proceedings of the 2001 International Conference on Parallel Processing
Compositional Technique for Synthesising Multi-Phase Regular Arrays
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Iterative Optimization in the Polyhedral Model: Part I, One-Dimensional Time
Proceedings of the International Symposium on Code Generation and Optimization
Iterative optimization in the polyhedral model: part ii, multidimensional time
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
A practical automatic polyhedral parallelizer and locality optimizer
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Hierarchical Composite Regular Parallel Architecture
ISPDC '09 Proceedings of the 2009 Eighth International Symposium on Parallel and Distributed Computing
Scalable array SSA and array data flow analysis
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
| Hi-index | 0.00 |
Hybrid multiprocessor architectures which combine re-configurable computing and multiprocessors on a chip are being proposed to transcend the performance of standard multi-core parallel systems. Both fine-grained and coarse-grained parallel algorithm implementations are feasible in such hybrid frameworks. A compositional strategy for designing fine-grained multi-phase regular processor arrays to target hybrid architectures is presented in this paper. The method is based on deriving component designs using classical regular array techniques and composing the components into a unified global design. Effective designs with phase-changes and data routing at run-time are characteristics of these designs. In order to describe the data transfer between phases, the concept of communication domain is introduced so that the producer-consumer relationship arising from multi-phase computation can be treated in a unified way as a data routing phase. This technique is applied to derive new designs of multi-phase regular arrays with different dataflow between phases of computation.