Original Article: Simulation-based weight factor selection and FPGA prediction core implementation for finite-set model based predictive control of power electronics

  • Authors:
  • Thomas J. Vyncke;Steven Thielemans;Jan A. A. Melkebeek

  • Affiliations:
  • Department of Electrical Energy, Systems and Automation (EESA), Ghent University (UGent), Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium;Department of Electrical Energy, Systems and Automation (EESA), Ghent University (UGent), Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium;Department of Electrical Energy, Systems and Automation (EESA), Ghent University (UGent), Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium

  • Venue:
  • Mathematics and Computers in Simulation
  • Year:
  • 2013

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Abstract

Model-based predictive control (MBPC) for power-electronic converters offers fast and accurate control. Based on the prediction of the future system states the optimal control input sequence is obtained by calculating a cost for each sequence. The control objectives are expressed as terms in the cost function which are weighted to divide the control effort. However, selecting good values for the weight factors is not a trivial task. In this paper a method is discussed for the weight factor selection based on extensive system simulations. The simulation approach for the hybrid system of power electronic converter and its load is discussed as well. In this paper a specific application is considered: the combined output current and capacitor voltage control of a 4-level flying-capacitor converter (FCC). This inverter topology possesses important advantages, but the control is also challenging. The high computational burden of MBPC is often restrictive for a good implementation. In this paper the implementation in a field-programmable gate array (FPGA) of an efficient prediction and optimization calculation core for finite-set MBPC is discussed. The core is fully implemented in programmable digital logic and a good performance is obtained by exploiting the strong points of the FPGA: parallelism and pipe-lining. The calculation core can be used in three applications: for hardware co-simulations, for hardware acceleration with processor-based implementations and for full FPGA implementations. Experimental results obtained with an FPGA implementation are presented.