Cache coherence for GPU architectures

Authors:
Inderpreet Singh;Arrvindh Shriraman;Wilson W. L. Fung;Mike O'Connor;Tor M. Aamodt
Affiliations:
University of British Columbia, Canada;Simon Fraser University, Canada;University of British Columbia, Canada;Advanced Micro Devices, Inc. (AMD), USA;University of British Columbia, Canada
Venue:
HPCA '13 Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Year:
2013

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Abstract

While scalable coherence has been extensively studied in the context of general purpose chip multiprocessors (CMPs), GPU architectures present a new set of challenges. Introducing conventional directory protocols adds unnecessary coherence traffic overhead to existing GPU applications. Moreover, these protocols increase the verification complexity of the GPU memory system. Recent research, Library Cache Coherence (LCC) [34, 54], explored the use of time-based approaches in CMP coherence protocols.