Universal Numerical Encoder and Profiler Reduces Computing's Memory Wall with Software, FPGA, and SoC Implementations

  • Authors:
  • Al Wegener

  • Affiliations:
  • -

  • Venue:
  • DCC '13 Proceedings of the 2013 Data Compression Conference
  • Year:
  • 2013

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Abstract

Numerical computations have accelerated significantly since 2005 thanks to two complementary, silicon-enabled trends: multi-core processing and single instruction, multiple data (SIMD) accelerators. Unfortunately, due to fundamental limitations of physics, these two trends could not be accompanied by a corresponding increase in memory, storage, and I/O bandwidth. We describe Application Acceleration (APAX) numerical encoding, a computationally efficient, adaptive method that lowers the memory wall for high-performance computing (HPC) datasets. APAXI has been implemented in both software and hardware. On 24 HPC datasets, APAX achieved encoding rates between 3:1 and 10:1 without changing the dataset's statistical or spectral characteristics.