A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
An algebraic approach to network coding
IEEE/ACM Transactions on Networking (TON)
New Systolic Architectures for Inversion and Division in GF(2^m)
IEEE Transactions on Computers
FPGA implementation of a high speed network interface card for optical burst switched networks
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Trading structure for randomness in wireless opportunistic routing
Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
Improving FPGA routability using network coding
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Fast elliptic curve cryptography on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA implementation(s) of a scalable encryption algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Symbol-level network coding for wireless mesh networks
Proceedings of the ACM SIGCOMM 2008 conference on Data communication
Efficient Parallelized Network Coding for P2P File Sharing Applications
GPC '09 Proceedings of the 4th International Conference on Advances in Grid and Pervasive Computing
Random network coding on the iPhone: fact or fiction?
Proceedings of the 18th international workshop on Network and operating systems support for digital audio and video
Pushing the Envelope: Extreme Network Coding on the GPU
ICDCS '09 Proceedings of the 2009 29th IEEE International Conference on Distributed Computing Systems
FPGA implementation of highly parallelized decoder logic for network coding (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Galois field hardware architectures for network coding
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
On Improving Parallelized Network Coding with Dynamic Partitioning
IEEE Transactions on Parallel and Distributed Systems
Distributed source coding for satellite communications
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
A Random Linear Network Coding Approach to Multicast
IEEE Transactions on Information Theory
Exploiting SIMD parallelism on dynamically partitioned parallel network coding for P2P systems
Computers and Electrical Engineering
Network coding based bulk data synchronization in mobile ad hoc networks
Proceedings of the 9th Asian Internet Engineering Conference
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Network coding is a well-known technique used to enhance network throughput and reliability by applying special coding to data packets. One critical problem in practice, when using the random linear network coding technique, is the high computational overhead. More specifically, using this technique in embedded systems with low computational power might cause serious delays due to the complex Galois field operations and matrix handling. To this end, this article proposes a high-performance decoding logic for random linear network coding using field-programmable gate-array (FPGA) technology. We expect that the inherent reconfigurability of FPGAs will provide sufficient performance as well as programmability to cope with changes in the specification of the coding. The main design motivation was to improve the decoding delay by dividing and parallelizing the entire decoding process. Fast arithmetic operations are achieved by the proposed parallelized GF ALUs, which allow calculations with all the elements of a single row of a matrix to be performed concurrently. To improve the flexibility in the utilization of the FPGA components, two different decoding methods have been designed and compared. The performance of the proposed idea is evaluated by comparing with the performance of the decoding process executed by general-purpose processors through an equivalent software algorithm. Overall, a maximum throughput of 65.98 Mbps is achieved with the proposed FPGA design on an XC5VLX110T Virtex 5 device. In addition, the proposed design provides speedups of up to 13.84 compared to an aggressively parallelized software decoding algorithm run on a quad-core AMD processor. Moreover, the design affords 12 times higher power efficiency in terms of throughput per watt than an ARM Coretex-A9 processor.