Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
IEEE Communications Magazine
Nonlinear estimation of PSK-modulated carrier phase with application to burst digital transmission
IEEE Transactions on Information Theory
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This work presents a new efficient parallel carrier recovery architecture suitable for ultrahigh speed intradyne coherent optical receivers (e.g., ≥100Gb/s) with quadrature amplitude modulation (QAM). The proposed scheme combines a novel low-latency parallel digital phase locked loop (DPLL) with a feedforward carrier phase recovery (CPR) algorithm. The new low-latency parallel DPLL is designed to compensate not only carrier frequency offset but also frequency fluctuations such as those induced by mechanical vibrations or power supply noise. Such carrier frequency fluctuations must be compensated since they lead to higher phase error variance in traditional feedforward CPR techniques, significantly degrading the receiver performance. In order to enable a parallel-processing implementation in multigigabit per second receivers, a new approximation to the DPLL computation is introduced. The proposed technique reduces the latency within the feedback loop of the DPLL introduced by parallel processing, while at the same time it provides a bandwidth and capture range close to those achieved by a serial DPLL. Simulation results demonstrate that the effects caused by frequency deviations can be eliminated with the proposed lowlatency parallel carrier recovery architecture.