Theoretical Computer Science
Proceedings of the 26th International Conference on Software Engineering
Joint structural and temporal property specification using timed story scenario diagrams
FASE'07 Proceedings of the 10th international conference on Fundamental approaches to software engineering
Verifying functional behaviors of automotive products in EAST-ADL2 using UPPAAL-PORT
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
A timed automata-based method to analyze EAST-ADL timing constraint specifications
ECMFA'12 Proceedings of the 8th European conference on Modelling Foundations and Applications
ICECCS '12 Proceedings of the 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems
ViTAL: A Verification Tool for EAST-ADL Models Using UPPAAL PORT
ICECCS '12 Proceedings of the 2012 IEEE 17th International Conference on Engineering of Complex Computer Systems
TimeSquare: treat your models with logical time
TOOLS'12 Proceedings of the 50th international conference on Objects, Models, Components, Patterns
MODELS'07 Proceedings of the 10th international conference on Model Driven Engineering Languages and Systems
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It is critical to analyze characteristics of real-time embedded systems, such as timing behavior, early in the development. In the automotive domain, EAST-ADL is a concrete example of the model-based approach for the architectural modeling of real-time systems. The Timing Augmented Description Language v2 (TADL2) allows for the specification of timing constraints on top of EAST-ADL models. In this paper we propose a formal validation & verification methodology for timing behaviors given with TADL2. The formal semantics of the timing constraints is given as a mapping to the Clock Constraint Specification Language (CCSL), a formal language that implements the MARTE Time Model. Based on such a mapping, the validation is carried out by the simulation of TADL2 specifications. The simulation allows for a rapid prototyping of TADL2 specifications. The verification is performed based on a TADL2 mapping to timed automata modeling using the Uppaal model-checker. The whole process is illustrated on a Brake-By-Wire application.