VHDL quality: synthesizability, complexity and efficiency evaluation

  • Authors:
  • M. Mastretti

  • Affiliations:
  • Italtel SIT, 20019 Settimo Milanese (MI) University of Milano, Computer Science Department

  • Venue:
  • EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
  • Year:
  • 1995

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Abstract