The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
The PARSEC benchmark suite: characterization and architectural implications
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
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Chip Multiprocessors (CMP) are there to stay in everyday computing -- starting from large scale server to mobile handheld devices. The challenge in designing a system with CMP is to utilize the processor resources optimally so that the power and performance goals are met. In this paper we present Threadguide, a framework for application adaptation augmenting mircoarchitectual support in CMP. The hardware assisted methodology collects runtime information from the program to annotate the code in appropriate locations. In subsequent passes compiler generate more refined code (thereby adapting the application) that distributes the workload across available processors and takes decisions to manage total energy to meet the power budget. The hardware is non-intrusive to the processor pipeline and does not hinder the execution of the processor. We show that with minimum hardware real estate (as low as a kilobyte) and energy overhead (less than 1% of dynamic energy), proposed scheme saves up to 18% in energy-delay product (EDP).