Chaotic noise MOS generator based on logistic map
Microelectronics Journal
Truly random number generators based on non-autonomous continuous-time chaos
International Journal of Circuit Theory and Applications
Chaotic pulse-position baseband modulation for an ultra-wideband transceiver in CMOS
IEEE Transactions on Circuits and Systems II: Express Briefs
Randomness enhancement using digitalized modified logistic map
IEEE Transactions on Circuits and Systems II: Express Briefs
A robust random number generator based on a differential current-mode chaos
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100x higher maximum Lyapunov exponent than the original jerk-equation based chaotic systems. The resulting chaotic output is shown to pass the NIST SP. 800-22 statistical test suite for pseudo-random number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59Gbits/s for the native chaotic output and 8.77Gbits/s for the resulting pseudo-random number generators.