Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Estimation of circuit activity considering signal correlations and simultaneous switching
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A methodology for efficient estimation of switching activity in sequential logic circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact and approximate methods for calculating signal and transition probabilities in FSMs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Statistical estimation of the switching activity in digital circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Simulation Modeling and Analysis
Simulation Modeling and Analysis
Estimation of sequential circuit activity considering spatial and temporal correlations
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Inaccuracies in power estimation during logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power analysis for sequential circuits at logic level
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Effects of correlations on accuracy of power analysis—an experimental study
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Statistical estimation of average power dissipation in sequential circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Accurate power estimation for large sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Stream synthesis for efficient power simulation based on spectral transforms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on systematic trade-off analysis in signal processing systems design
Power estimation starategies for a low-power security processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power Estimation Under Uncertain Delays
Integrated Computer-Aided Engineering
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Total power modeling in FPGAs under spatial correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: In this paper, we present a Monte Carlo based technique to estimate signal activity at the internal nodes of sequential logic circuits. The technique takes spatial and temporal correlations of logic signals into consideration. The Monte Carlo based techniques that have been proposed for combinational circuits can not be directly applied to sequential circuits due to the initial transient problem. The proposed approach deals with this problem by gaining insight from Markov chain theory. Experimental results show that the error (%) of estimated activity of individual nodes is within 3% in comparison to that of long run simulation results.