An arithmetic controller design for numerical control

Authors:
Shu-Chung Yi;Chin-Fa Hsieh
Affiliations:
Department of Computer Science and Information Engineering, National Changhua University of Education, No. 2, Shi-Da Road, Changhua 500, Taiwan, ROC and Department of Computer Science and Informat ...;Department of Electronic Engineering, China University of Science and Technology, No. 245, Sec. 3, Academia Rd., Nangang Dist., Taipei City 11581, Taiwan, ROC
Venue:
Computers and Electrical Engineering
Year:
2013

Citing 7
Cited 0

Computational and experimental environments for fuzzy logic and control

Computers and Electrical Engineering - Special issue on neural networks and fuzzy logic: theory and applications in robotics and manufacturing
Computer organization and design (2nd ed.): the hardware/software interface

Computer organization and design (2nd ed.): the hardware/software interface
Digital Computer Electronics

Digital Computer Electronics
The Verilog Procedural Interface for the Verilog Hardware Description Language

IVC '96 Proceedings of the 1996 IEEE International Verilog HDL Conference (IVC '96)
1.1: Integrating of Verilog-HDL and VHDL Languages in the SMASH (tm) Mixed-signal Multi-level Simulator

IVC-VIUF '98 Proceedings of the International Verilog HDL Conference and VHDL International Users Forum
A new construction adder based on Chinese abacus algorithm

Computers and Electrical Engineering
Adaptive high gain observer based output feedback predictive controller for induction motors

Computers and Electrical Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper provides an arithmetic controller comprising: an arithmetic logic unit having a plurality of arithmetic instructions, such as ADD (Addition), SUB (Subtraction), MUL (Multiplication), and DIV (Division) instructions. This arithmetic processor was implemented by a cell-based flow and supports the basic mathematical operations, and numerical control. All mathematical instructions are composed of three bytes. In the first byte, it contains the operation code and the address of the operand, while the operands are in the second and third bytes. While the processor architecture compared with the conventional CPU, the performance is speed up for the number reduction of instruction cycle. The number of instruction cycle is decreased to five T-states. All of these circuits were implemented by the TSMC 0.35@mm cell library. A 20-pin I/O PAD was selected to package this processor. The experimental results are showed and discussions are made.