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Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the International Technology Roadmap for Semiconductors annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the operating frequency of RF devices increases, the size of Si integrated antenna will decrease and it is feasible to employ them as a revolutionary interconnect for intra-chip wireless communications. In this paper, we focus on physical requirements and design challenges of wireless NoC. It is demonstrated that employing an optimum-radiation phased array antenna and multihop communications will increase the reliability of on-chip wireless links by several orders of magnitude using a limited power budget less than 0.1pJ/bit.