Optimal Left-to-Right Binary Signed-Digit Recoding
IEEE Transactions on Computers - Special issue on computer arithmetic
Generalized WLS method for designing all-pass variable fractional-delay digital filters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Minimax design of low-complexity allpass variable fractional-delay digital filters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Applications of simulated annealing for the design of specialdigital filters
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Design of Allpass Variable Fractional Delay Filter
IEEE Transactions on Signal Processing
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This paper investigates the optimal design of allpass variable fractional delay (VFD) filters with coefficients expressed as sums of signed powers-of-two terms, where the weighted integral squared error is the cost function to be minimized. The design can be classified as an integer programming problem. To solve this problem, a new procedure is proposed to generate a reduced discrete search region to decrease the computational complexity. A new exact penalty function method is developed to solve the optimal design problem for allpass VFD filter with signed powers-of-two coefficients. Design examples show that the proposed method can achieve a higher accuracy when compared with the quantization method.