Parabolic bursting in an excitable system coupled with a slow oscillation
SIAM Journal on Applied Mathematics
Type i membranes, phase resetting curves, and synchrony
Neural Computation
A Cellular Structure for Online Routing of Digital Spiking Neuron Axons and Dendrites on FPGAs
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
FCCM '12 Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
Simple model of spiking neurons
IEEE Transactions on Neural Networks
Which model to use for cortical spiking neurons?
IEEE Transactions on Neural Networks
ICANN'12 Proceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I
A large-scale spiking neural network accelerator for FPGA systems
ICANN'12 Proceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic
IEEE Transactions on Computers
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The Inferior-Olivary nucleus (ION) is a well-charted region of the brain, heavily associated with sensorimotor control of the body. It comprises ION cells with unique properties which facilitate sensory processing and motor-learning skills. Various simulation models of ION-cell networks have been written in an attempt to unravel their mysteries. However, simulations become rapidly intractable when biophysically plausible models and meaningful network sizes (=100 cells) are modeled. To overcome this problem, in this work we port a highly detailed ION cell network model, originally coded in Matlab, onto an FPGA chip. It was first converted to ANSI C code and extensively profiled. It was, then, translated to HLS C code for the Xilinx Vivado toolflow and various algorithmic and arithmetic optimizations were applied. The design was implemented in a Virtex 7 (XC7VX485T) device and can simulate a 96-cell network at real-time speed, yielding a speedup of x700 compared to the original Matlab code and x12.5 compared to the reference C implementation running on a Intel Xeon 2.66GHz machine with 20GB RAM. For a 1,056-cell network (non-real-time), an FPGA speedup of x45 against the C code can be achieved, demonstrating the design's usefulness in accelerating neuroscience research. Limited by the available on-chip memory, the FPGA can maximally support a 14,400-cell network (non-real-time) with online parameter configurability for cell state and network size. The maximum throughput of the FPGA ION-network accelerator can reach 2.13 GFLOPS.