Resource Trade-offs in Syntactically Multilinear Arithmetic Circuits

  • Authors:

  • Maurice Jansen;Meena Mahajan;B. V. Rao

  • Affiliations:

  • Laboratory for Foundations of Computer Science, School of Informatics, The University of Edinburgh, Edinburgh, UK;The Institute of Mathematical Sciences, Chennai, India 600113;Universität des Saarlandes, Informatik, Saarbrücken, Germany 66041

  • Venue:
  • Computational Complexity
  • Year:
  • 2013

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Abstract

The class of polynomials computable by polynomial size log-depth arithmetic circuits (VNC 1) is known to be computable by constant width polynomial degree circuits (VsSC 0), but whether the converse containment holds is an open problem. As a partial answer to this question, we give a construction which shows that syntactically multilinear circuits of constant width and polynomial degree can be depth-reduced, which in our notation shows that sm-VsSC 0 $${\subseteq}$$ 驴 sm-VNC 1. We further strengthen this inclusion, by giving a separate construction that provides a width-efficient simulation for constant width syntactically multilinear circuits by constant width syntactically multilinear algebraic branching programs; in our notation, sm-VsSC 0 $${\subseteq}$$ 驴 sm-VBWBP. We then focus on polynomial size syntactically multilinear circuits and study relationships between classes of functions obtained by imposing various resource (width, depth, degree) restrictions on these circuits. Along the way, we also observe a characterization of the class NC 1 in terms of a restricted class of planar branching programs of polynomial size. Finally, in contrast to the general case, we report closure and stability of coefficient functions for the syntactically multilinear classes studied in this paper.