Mismatch Characterization of Submicron MOS Transistors

  • Authors:

  • J. Bastos;M. Steyaert;A. Pergoot;W. Sansen

  • Affiliations:

  • Department of Electrical Engineering, Katholieke Universiteit Leuven, ESAT-MICAS, Heverlee, Belgium 3001;Department of Electrical Engineering, Katholieke Universiteit Leuven, ESAT-MICAS, Heverlee, Belgium 3001;Alcatel Mietec, Oudenaarde, Belgium 9700;Department of Electrical Engineering, Katholieke Universiteit Leuven, ESAT-MICAS, Heverlee, Belgium 3001

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 1997

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Abstract

The characterization of transistor mismatch in a standard0.7 碌m CMOS technology is presented. A new methodfor matching parameter extraction has been used. Mismatch parametersbased on measurements on 10000 nMOS and 10000 pMOS transistorshave been extracted. It is observed that the threshold voltagemismatch linear dependency on the inverse of the square rootof the effective channel area no longer holds for transistorsof 0.7 碌m channel length. An extended model basedon the physical causes of threshold voltage mismatch is proposed.Contrary to the established theory, it is observed that transistorswith channel length below 1 碌m have less currentmismatch than what is predicted by a linear relationship withthe channel area.