Storage allocation for embedded processors
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Heterogeneous memory management for embedded systems
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Exploiting shared scratch pad memory space in embedded multiprocessor systems
Proceedings of the 39th annual Design Automation Conference
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Banked scratch-pad memory management for reducing leakage energy consumption
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Shared Scratch-Pad Memory Space Management
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Dynamic allocation for scratch-pad memory using compile-time decisions
ACM Transactions on Embedded Computing Systems (TECS)
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Heap data allocation to scratch-pad memory in embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
A low-power phase change memory based hybrid cache architecture
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 45th annual Design Automation Conference
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
A durable and energy efficient main memory using phase change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
PDRAM: a hybrid PRAM and DRAM main memory system
Proceedings of the 46th Annual Design Automation Conference
PCRAMsim: system-level performance, energy, and area modeling for phase-change ram
Proceedings of the 2009 International Conference on Computer-Aided Design
Write activity reduction on flash main memory via smart victim cache
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
Energy- and endurance-aware design of phase change memory caches
Proceedings of the Conference on Design, Automation and Test in Europe
A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)
Proceedings of the Conference on Design, Automation and Test in Europe
Increasing PCM main memory lifetime
Proceedings of the Conference on Design, Automation and Test in Europe
Compilation of stream programs for multicore processors that incorporate scratchpad memories
Proceedings of the Conference on Design, Automation and Test in Europe
Power and performance of read-write aware hybrid caches with non-volatile memories
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing write activities to non-volatile memory via scheduling and recomputation
SASP '10 Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors (SASP)
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory
Proceedings of the 48th Design Automation Conference
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
DSN '11 Proceedings of the 2011 IEEE/IFIP 41st International Conference on Dependable Systems&Networks
Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems
ICPP '11 Proceedings of the 2011 International Conference on Parallel Processing
Benchmarking modern multiprocessors
Benchmarking modern multiprocessors
Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
IPDPSW '12 Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum
MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory
INTERACT '12 Proceedings of the 2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT)
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory
Journal of Signal Processing Systems
| Hi-index | 0.00 |
The recent emergence of various Non-Volatile Memories (NVMs), with many attractive characteristics such as low leakage power and high-density, provides us with a new way of addressing the memory power consumption problem. In this article, we target embedded CMPs, and propose a novel Hybrid Scratch Pad Memory (HSPM) architecture which consists of SRAM and NVM to take advantage of the ultra-low leakage power, high density of NVM, and fast access of SRAM. A novel data allocation algorithm as well as an algorithm to determine the NVM/SRAM ratio for the novel HSPM architecture are proposed. The experimental results show that the data allocation algorithm can reduce the memory access time by 33.51% and the dynamic energy consumption by 16.81% on average for the HSPM architecture when compared with a greedy algorithm. The NVM/SRAM size determination algorithm can further reduce the memory access time by 14.7% and energy consumption by 20.1% on average.