Adaptive Cache Compression for High-Performance Processors
Proceedings of the 31st annual international symposium on Computer architecture
ACM SIGARCH Computer Architecture News
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Rethinking DRAM design and organization for energy-constrained multi-cores
Proceedings of the 37th annual international symposium on Computer architecture
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing
IEEE Design & Test
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Proceedings of the 49th Annual Design Automation Conference
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
Multi-level cell STT-RAM: is it realistic or just a dream?
Proceedings of the International Conference on Computer-Aided Design
Layout-aware optimization of STT MRAMs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we study the use of multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) in cache design of embedded systems and microprocessors. Compared to the single level cell (SLC) design, a MLC STT-RAM cache is expected to offer higher density and faster system performance. However, the cell design constrains, such as the switching current requirement and asymmetry in write operations, severely limit the density benefit of the conventional MLC STT-RAM. The two-step read/write accesses and inflexible data mapping strategy in the existing MLC STT-RAM cache architecture may even result in system performance degradation. To unleash the real potential of MLC STT-RAM cache, we propose a cross-layer solution. First, we introduce the reverse magnetic junction tunneling (MTJ) into MLC cell design, which offers a more balanced device and design tradeoff and enables 2x storage density than SLC. At architectural level, we propose a cell split mapping method to divide cache lines into fast and slow regions and data migration policies to allocate the frequently-used data to fast regions. Furthermore, an application-aware speed enhancement mode is utilized to adaptively trade-off cache capacity and speed, satisfying different requirements of various applications. Simulation results show that the proposed techniques can improve the system performance by 10.3% and reduce the energy consumption on cache by 26.0% compared with conventional MLC STT-RAM.