FPGA implementation of the JPEG2000 binary arithmetic (MQ) decoder

  • Authors:
  • David J. Lucking;Eric J. Balster;Kerry L. Hill;Frank A. Scarpino

  • Affiliations:
  • Air Force Research Laboratory (AFRL), Wright Patterson, United States;The University of Dayton (UD), Dayton, United States;Air Force Research Laboratory (AFRL), Wright Patterson, United States;Air Force Research Laboratory (AFRL), Wright Patterson, United States

  • Venue:
  • Journal of Real-Time Image Processing
  • Year:
  • 2013

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Abstract

A flexible FPGA implementation of the JPEG-2000 binary arithmetic decoder is presented in this paper. The proposed JPEG2000 binary arithmetic decoder reduces the amount of resources used on the FPGA allowing 19% more entropy block decoders to fit on chip and consequently increasing the throughput by 21% beyond previous designs.