Reduced Power Dissipation Through Truncated Multiplication
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Protocols for RFID tag/reader authentication
Decision Support Systems
IEEE Transactions on Dependable and Secure Computing
Providing Stronger Authentication at a Low Cost to RFID Tags Operating under the EPCglobal Framework
EUC '08 Proceedings of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing - Volume 02
RFID mutual authentication protocols
Decision Support Systems
High-accuracy fixed-width modified booth multipliers for lossy applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EMAP: an efficient mutual-authentication protocol for low-cost RFID tags
OTM'06 Proceedings of the 2006 international conference on On the Move to Meaningful Internet Systems: AWeSOMe, CAMS, COMINF, IS, KSinBIT, MIOS-CIAO, MONET - Volume Part I
Fast truncated multiplication for cryptographic applications
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Fibonacci and Galois representations of feedback-with-carry shift registers
IEEE Transactions on Information Theory
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Radio-frequency identification (RFID) is a recent technology that utilizes radio frequencies to track the object by transmitting a signal with a unique serial identity. Generally, the drawbacks of RFID technology are high cost and authentication systems between a reader and a tag become weak. In this paper, we proposed a protocol for RFID tag-reader mutual authentication scheme which is hardware efficient and consumes less dynamic power. Truncated multipliers are implemented in RFID tag-reader mutual authentication protocol system due to reduction in hardware cost and dynamic power. Experimental evaluation reveals that the proposed protocol with truncated multipliers provides more security than the earlier schemes. The proposed protocol is described in VHDL and simulated using Altera Quartus II. The functional block is implemented as hardware using an Altera DE2 Cyclone II (EP2C35F672C6) Field-Programmable Gate Array (FPGA).