Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Making DRAM Refresh Predictable
ECRTS '10 Proceedings of the 2010 22nd Euromicro Conference on Real-Time Systems
Design and Implementation of a DDR3-based Memory Controller
ISDEA '13 Proceedings of the 2013 Third International Conference on Intelligent System Design and Engineering Applications
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With the increasing bandwidth demand in system technologies, several generations of memory have been optimized in order to guarantee higher QoS and better performance. Dynamic memory has various advantages in terms of frequency and bandwidth but the periodic refresh operation remains its principle weakness which reduces the chance of its use in reliable hardware real time systems. In spite of the refreshment important role to prevent data loss, this operation decreases predictability and bandwidth by about 3% in dynamic memories. We propose a memory controller which guarantees the refreshment of our DDR3 memory during the write operation. We choose to write in predefined address following a barrel shifter technique. This idea represents the key solution to visit all the rows within the maximum required refresh time. This technique is an original solution to preserve memory write, read and refresh reliability.