Fractal and Wavelet Image Compression Techniques
Fractal and Wavelet Image Compression Techniques
Hide and Seek: An Introduction to Steganography
IEEE Security and Privacy
Design and implementation of a secret key steganographic micro-architecture employing FPGA
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Adaptive Steganography based on textures
CONIELECOMP '07 Proceedings of the 17th International Conference on Electronics, Communications and Computers
A Secure Image Steganography using LSB, DCT and Compression Techniques on Raw Images
ICISIP '05 Proceedings of the 2005 3rd International Conference on Intelligent Sensing and Information Processing
FPGA Hardware Architecture of the Steganographic ConText Technique
CONIELECOMP '08 Proceedings of the 18th International Conference on Electronics, Communications and Computers (conielecomp 2008)
Performance comparison of DCT and Walsh transform for steganography
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
A DWT Based Approach for Steganography Using Biometrics
DSDE '10 Proceedings of the 2010 International Conference on Data Storage and Data Engineering
Optimized transmission of JPEG2000 streams over wireless channels
IEEE Transactions on Image Processing
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Steganography is a powerful method to conceal the existence of secret data inside a cover object. The concealment steps are performed in the spatial domain and/or the transform domain such as wavelet transform. While it is harder to detect, the transform domain steganography involves complex computations. Hence implementing steganography in hardware improves the steganography system performance. The preservation of the entire secret information is one of the main challenges for the transform domain steganography. Errors, introduced by quantisation steps, destroy some of the embedded secret bits. In this paper, we present a novel algorithm to embed and extract the entire secret data in the Haar wavelet-based transform without any secret information loss. This is accomplished by special clipping mechanism as well as modifying the placement of the secret bit in the transform coefficients. The algorithm is implemented in an FPGA-based hardware, and its performance metrics are examined including resources utilisation, power, timing and energy.