Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration
Microelectronic Engineering
Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits
Microelectronics Journal
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal-oxide-semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75^o, 80^o, 85^o and 90^o. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80^o for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5@mm), dielectric liner thickness (from 0.1 to 0.5@mm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50@mm) and acceptor concentration (from 1x10^1^5 to 5x10^1^5cm^-^3) cause increase of T-TSV capacitance by about 25fF, -12fF, 12fF, 210fF and 12fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.