A switching-based phase noise model for CMOS ring oscillators based on multiple thresholds crossing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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In a ring oscillator, the behaviour in which the output voltage ramp (up/down) of its individual delay cell crosses the threshold, which triggers the next stage delay cell, is crucial in determining the timing jitter, and hence phase noise. Specifically, as the slew rate of the ramp decreases and/or the amount of noise contribution from the transistors in the delay cell increases, the voltage ramp (up or down) has a higher probability of crossing the threshold multiple times, before finally passing it at a time denoted as last passage time, which is more accurate than the conventional first passage time model. This multiple crossing results in a higher jitter. In the past, investigation in last passage time jitter model results in jitter expression that can only be calculated numerically and thus no design guidelines/insights are apparent. In this paper, a novel model is presented with a simple closed form formula, which shows the extra jitter, due to multiple crossing, adds a term that increases as a function of the fourth power of the noise strength/slew rate ratio. The formula is applied to a real life practical low slow rate/high noise ring oscillator which finds application, for example, in random number generator implementation. Corresponding transistor level simulation results agree reasonably well with the model. Furthermore, it is shown that, on example designs, the last passage time approach in this paper can lead to time jitter that is 100 % larger than that due to conventional first passage time model.