Synchronized CSMA contention: model, implementation, and evaluation

  • Authors:

  • Ehsan Aryafar;Theodoros Salonidis;Jingpu Shi;Edward Knightly

  • Affiliations:

  • Department of Electrical Engineering, Princeton University, Princeton, NJ;IBMT. J. Watson Research Center, Yorktown Heights, NY;Doliver Capital Advisors L.P., Houston, TX;Department of Electrical and Computer Engineering, Rice University, Houston, TX

  • Venue:
  • IEEE/ACM Transactions on Networking (TON)
  • Year:
  • 2013

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Abstract

A class of carrier sense multiple access (CSMA) protocols used in a broad range of wireless applications uses synchronized contention where nodes periodically contend at intervals of fixed duration. While several models exist for asynchronous CSMA contention used in protocols like IEEE 802.11 MAC, no model exists for synchronized CSMA contention that also incorporates realistic factors like clock drifts. In this paper, we introduce a model that quantifies the interplay of clock drifts with contention window size, control packet size, and carrier sense regulated by usage of guard time. Using a field programmable gate array (FPGA)-based MAC protocol implementation and controlled experiments on a wireless testbed, we evaluate the model predictions on the isolated and combined impact of these key performance factors to per-flow throughput and fairness properties in both single-hop and multihop networks. Our model and experimental evaluation reveal conditions on protocol parameters under which the throughput of certain flows can exponentially decrease; while at the same time, it enables solutions that can offset such problems in a predictable manner.