International Journal of Computer Vision
IEEE Transactions on Pattern Analysis and Machine Intelligence
SIGGRAPH '78 Proceedings of the 5th annual conference on Computer graphics and interactive techniques
Real Time Face and Object Tracking as a Component of a Perceptual User Interface
WACV '98 Proceedings of the 4th IEEE Workshop on Applications of Computer Vision (WACV'98)
Mean Shift Analysis and Applications
ICCV '99 Proceedings of the International Conference on Computer Vision-Volume 2 - Volume 2
ACM Computing Surveys (CSUR)
A dynamic reconfigurable hardware/software architecture for object tracking in video streams
EURASIP Journal on Embedded Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Moments and Moment Invariants in Pattern Recognition
Moments and Moment Invariants in Pattern Recognition
Object tracking on FPGA-based smart cameras using local oriented energy and phase features
Proceedings of the Fourth ACM/IEEE International Conference on Distributed Smart Cameras
The estimation of the gradient of a density function, with applications in pattern recognition
IEEE Transactions on Information Theory
Low-latency histogram equalization for infrared image sequences: a hardware implementation
Journal of Real-Time Image Processing
Hi-index | 0.00 |
In this paper, we propose a CAMShift inspired object tracker for VGA resolution images implemented in an FPGA with a view to using low-cost commercially available CMOS sensors. We discuss architectural issues that arise in trying to meet the dual constraints of serialised input from a camera, and the requirement for iterative computation in the mean shift inner loop. We argue that a system oriented toward vector processing allows us to both meet our timing requirements on the sensor side and perform multiple steps of gradient ascent on the algorithm side, thus mitigating the negative effect of low input bandwidth and allowing iterative algorithms to operate within the frame acquisition time. We show how this can be implemented as a stream process with relatively low memory overhead in an Altera Cyclone IV EP4CE115F29C7FPGA found on the DE2-115 development board paired with a Terasic D5M digital camera.