A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-$$\Updelta\Upsigma$$ΔΣ ADC with 1.5 cycle quantizer delay and improved STF

Authors:
Sakkarapani Balagopal;Kehan Zhu;Vishal Saxena
Affiliations:
Electrical and Computer Engineering Department, Boise State University, Boise, USA 83725-2075;Electrical and Computer Engineering Department, Boise State University, Boise, USA 83725-2075;Electrical and Computer Engineering Department, Boise State University, Boise, USA 83725-2075
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2014

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Abstract

A 1 GS/s continuous-time delta-sigma modulator (CT- $$\Updelta\Upsigma$$ Δ Σ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $$\Updelta\Upsigma$$ Δ Σ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $$\Updelta\Upsigma$$ Δ Σ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.