High performance implementation of texture features extraction algorithms using FPGA architecture

Authors:
Ali Reza Akoushideh;Asadollah Shahbahrami;Babak Mazloom-Nezhad Maybodi
Affiliations:
Electrical and Computer Department, Shahid-Beheshti University, G.C, Tehran, Iran;Department of Computer Engineering, University of Guilan, Rasht, Iran;Electrical and Computer Department, Shahid-Beheshti University, G.C, Tehran, Iran
Venue:
Journal of Real-Time Image Processing
Year:
2014

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Abstract

The most popular second-order statistical texture features are derived from the co-occurrence matrix, which has been proposed by Haralick. However, the computation of both matrix and extracting texture features are very time consuming. In order to improve the performance of co-occurrence matrices and texture feature extraction algorithms, we propose an architecture on FPGA platform. In the proposed architecture, first, the co-occurrence matrix is computed then all thirteen texture features are calculated in parallel using computed co-occurrence matrix. We have implemented the proposed architecture on Virtex 5 fx130T-3 FPGA device. Our experimental results show that a speedup of 421[脳 yields over a software implementation on Intel Core i7 2.0 GHz processor. In order to improve much more performance on textures, we have reduced the computation of 13 texture features to 3 texture features using ranking of Haralick's features. The performance improvement is 484脳.