Design and simulation of a QCA 2 to 1 multiplexer
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
Adder and Multiplier Design in Quantum-Dot Cellular Automata
IEEE Transactions on Computers
Design and Test of Digital Circuits by Quantum-Dot Cellular Automata
Design and Test of Digital Circuits by Quantum-Dot Cellular Automata
Irreversibility and heat generation in the computing process
IBM Journal of Research and Development
Logical reversibility of computation
IBM Journal of Research and Development
Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA) multiplexers
International Journal of Circuit Theory and Applications
Implementation of a crossbar network using quantum-dot cellular automata
IEEE Transactions on Nanotechnology
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QCA (Quantum-dot Cellular Automata) is an alternative technology for CMOS that has a low power consumption and high density. QCA extensively supports the new plans in the field of nanotechnology. Applications of QCA technology as an alternative method for CMOS technology in nano-scale have a hopeful future. This paper presents the successful design, implementation and simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexer with the minimum area as compared to the previous models in QCA technology. In this paper, by means of 4 to 1 multiplexers including D-Flip Flop (D-FF) structure in QCA, we present an 8-bit universal shift register. The structure of the 8-bit universal register is extendable to 16-bit, 32-bit and etc. In this paper, the successful simulation of 2 to 1, 4 to 1 and 8 to 1 multiplexers, including D-FF and finally 8-bit universal register structure in QCADesigner is provided. The multiplexers and D-FF presented in this paper have the minimum complexity, area and delay compared to the previous models. In this paper, the implementation of 8-bit universal shift register, by means of 4 to 1 multiplexers and D-FF are presented in QCA technique which have the minimum complexity and delay. In the proposed design of the 8-bit universal shift register, the faults are likely to occur at 2 to 1 multiplexers and D-FF. In this article, 2 to 1 multiplexers and D-FF are investigated from the cell missing and possible defects. Considering the pipeline being the virtue of QCA, the 8-bit universal shift register has a high speed function. This 8-bit universal shift register may be used in the high speed processors as well as cryptography circuits.