Router plugins: a software architecture for next-generation routers
IEEE/ACM Transactions on Networking (TON)
High Performance Switches and Routers
High Performance Switches and Routers
Toward a Distributed Control Plane Architecture for Next Generation Routers
ECUMN '07 Proceedings of the Fourth European Conference on Universal Multiservice Networks
The IETF Multiprotocol Label Switching Standard: The MPLS Transport Profile Case
IEEE Internet Computing
Enabling architectures for qos provisioning
Enabling architectures for qos provisioning
A modularized control plane for BGP
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
A distributed and scalable RSVP-TE architecture for next generation IP routers
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
DROP: an open-source project towards distributed SW router architectures
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
A distributed and scalable routing table manager for the next generation of IP routers
IEEE Network: The Magazine of Global Internetworking
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One of the main concerns of network operators is that current routers are not scalable in order to meet future traffic requirements on the core Internet taking into account new applications. The next generation routers with petabit switching capacity are being built to serve higher demands. Their processing capability is enhanced by additional memory and computing resources on control and line cards with a very large number of high speed interfaces. However, the current routing software architecture is not able to fully exploit such an advanced hardware platform. This paper proposes a first distributed software architecture of MPLS/LDP targeting the next generation routers. We investigate the ability of offloading components of the current centralized architecture of MPLS/LDP on to line cards in order to share the load between the control and line cards. This allows the signaling to be achieved entirely at the line card level, hence, improving the robustness, scalability and resiliency of the system. Performance evaluation, considering the CPU utilization and the number of exchanged messages, is also presented.