Advanced 80386 programming techniques
Advanced 80386 programming techniques
80x86 architecture and programming (vol. II): architecture reference
80x86 architecture and programming (vol. II): architecture reference
PC Magazine programmer's technical reference: the processor and coprocessor
PC Magazine programmer's technical reference: the processor and coprocessor
A taxonomy of computer program security flaws
ACM Computing Surveys (CSUR)
A note on the confinement problem
Communications of the ACM
The Undocumented PC
Understanding X86 Microprocessors
Understanding X86 Microprocessors
Using the State Delta Verification System (SDVS) for Hardware Verification
Proceedings of the IFIP TC10/WG 10.2 International Conference on Theorem Provers in Circuit Design: Theory, Practice and Experience
The Intel 80x86 Processor Architecture: Pitfalls for Secure Systems
SP '95 Proceedings of the 1995 IEEE Symposium on Security and Privacy
Guest Editorial: Introduction to the Special Section
IEEE Transactions on Software Engineering
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Caisson: a hardware description language for secure information flow
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 38th annual international symposium on Computer architecture
Systematic security assessment at an early processor design stage
TRUST'11 Proceedings of the 4th international conference on Trust and trustworthy computing
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An in-depth analysis of the 80脳86 processor families identifies architectural properties that may have unexpected, and undesirable, results in secure computer systems. In addition, reported implementation errors in some processor versions render them undesirable for secure systems because of potential security and reliability problems. In this paper, we discuss the imbalance in scrutiny for hardware protection mechanisms relative to software, and why this imbalance is increasingly difficult to justify as hardware complexity increases. We illustrate this difficulty with examples of architectural subtleties and reported implementation errors.